Electronic devices are ubiquitous in society and can be found in everything from cell phones to computers. The complexity and sophistication of these electronic devices usually increases with each generation. For example, newer microprocessors often have higher operating frequencies than previous generations of microprocessors. As a result of the increased operating frequencies, newer generations of microprocessors may consume more power than previous generations of microprocessors.
In addition to the increased operating frequency potentially causing increased power consumption, this increased operating frequency also may cause a growing disparity between the speed that a computer's microprocessor operates at versus the computer's memory access speed. Because of this disparity, computers with high speed microprocessors may spend a large amount of time waiting for memory references to complete instead of performing computational operations. In addition, some microprocessors may attempt to execute multiple threads of program code concurrently to offset this downtime. Notwithstanding the increase in throughput of the program code that comes with multithreading, there still remains a need for providing methods and apparatuses that conserve power in single core or multi-core processors
Several techniques have been developed to address this increase in consumption of power of microprocessors. One such technique developed is to reduce the frequency in one or more cores of the microprocessor. In general, active power of a microprocessor is proportional to the operating frequency, i.e. reducing the number of clock edges seen by logic components in a microprocessor core reduces the active power consumed by the core. To reduce the operating frequency, sometimes referred to herein as “clock signal”, of a core, the microprocessor may introduce a clock skipping signal to the system clock signal to create a skip clock pattern. The clock skip pattern is periodic over some number of cycles, but functionally operates at a lower frequency than the unskipped, or free-running, clock signal. Thus, a core where a skipped clock signal is provided may consume less power than a core operating on a free running clock signal.
Other techniques to reduce the operating frequency may also be implemented in a microprocessor. For example, many microprocessors now incorporate dynamic voltage frequency scaling (DVFS) that is applied to one or more cores of the processor to reduce the power consumed by the microprocessor. In general, DVFS techniques adjust the operating voltage and/or the clock frequency at which the different cores of the microprocessor operate such that those cores consume less power. The scaling of the operating frequency of the one or more cores to a lower frequency may occur in response to the microprocessor detecting a lower processing requirement for the one or more cores.
As a result of the clock frequency reducing techniques described above, cores of a microprocessor may be operating at varying clock frequencies or on varying clock. For example, a first core may operate on a skipped clock signal, while a second core of the same microprocessor may operate on a free running clock signal. The operation of the cores of a microprocessor at varying frequencies often introduces synchronization issues for communication between programs being executed by the cores of the microprocessor and between the microprocessor and other components of a computer system. For example, data packets may be transmitted to a core or component operating on a skipped clock signal when the core is otherwise unable to read the transmitted packet, such as during a skipped clock cycle.
It is with these and other issues in mind that various aspects of the present disclosure were developed.